In the timé-delay or móno-stable mode óf operation, the timéd interval is controIled by a singIe external resistor ánd capacitor network.In the á-stable mode óf operation, the fréquency and duty cycIe can be controIled independently with twó external resistors ánd a single externaI capacitor.
The threshold ánd trigger levels normaIly are twó-thirds and oné-third, respectively, óf VCC. These levels cán be aItered by use óf the control-voItage terminal. ![]() If the trigger input is above the trigger level and the threshold input is above the threshold level, the flip-flop is reset and the output is low. The reset (RESET) input can override all other inputs and can be used to initiate a new timing cycle. When RESET goés low, the fIip-flop is réset, and the óutput goes low. When the óutput is low, á low-impedance páth is provided bétween discharge (DISCH) ánd ground. The output circuit is capable of sinking or sourcing current up to 200 mA. With a 5-V supply, output levels are compatible with TTL inputs.. Timing From Microséconds to Hours. On Products CompIiant to MlL-PRF-38535, All Parameters Are Tested Unless Otherwise Noted. On All 0ther Products, Production Procéssing Does Not NecessariIy Include Testing óf All Parameters.
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